The preferred embodiments relate to voltage controlled oscillator (VCO) technology and, more particularly, to a quadrature VCO (QVCO).
A VCO is a device (i.e., oscillator) that outputs an oscillating signal with a frequency that is controlled by the level of a bias voltage applied to the VCO. A fixed DC bias voltage to the VCO, therefore, should ideally produce a fixed output frequency signal, whereas that bias voltage also may be varied so as to vary the VCO output frequency. As to the latter, therefore, a modulating bias signal may be applied to cause the VCO to output a signal with a modulating frequency (or phase).
A certain type of modulation scheme that packs more than 1 bit/symbol for communicating data, and relevant to the preferred embodiments is quadrature phase-shift keying (QPSK). In QPSK, a VCO provides quadrature oscillating signals, thereby operating as a QVCO, where the quadrature signals consist of four different oscillating signals, each 90 degrees apart from the others. More specifically, as a type of phase-shift keying (PSK), QPSK communicates data by modulating (i.e., changing) a phase of a carrier signal. The term “quadrature” in QPSK indicates that there are four different phases, each preferably orthogonal with respect to one another, for the data modulation. More specifically, therefore, a single data quantity, or “symbol,” may be represented by any one of the four available phases, typically equispaced in the QPSK constellation at locations that are 90 degrees apart. Each location of these separate locations may represent a different one-of-four combination of two binary bits, thereby permitting communication of a symbol representing a binary value of 11, 01, 00, or 10. In QPSK, such data is modulated, and demodulated, typically by separating a bit stream into two separate bit streams, denoted as an in-phase stream designated as I and a quadrature phase designated as Q. The I data is modulated by a first signal (e.g., sine wave), while the Q data is modulated by a second signal that is 90 degrees apart (e.g., cosine wave) from the first signal, with the results added to provide the transmitted QPSK signal. Demodulation is achieved in a reverse process.
Given the preceding, of note in connection with QPSK methodology is that it involves quadrature phases, and in electronic circuits such phases are typically implemented using a VCO that is locked into quadratures, that is, having four different outputs that, as introduced earlier, are 90 degrees apart from one another. Such an architecture is typically referred to as a quadrature VCO, or abbreviated as QVCO. Further, quadrature local oscillation also may be used and be important in other applications, such as image rejection in receivers. By way of further background, therefore, two prior art QVCOs are described below.
FIG. 1 illustrates a schematic of a prior art parallel injection QVCO shown generally at 10. QVCO 10 includes bias control circuitry 12 that may be constructed according to known principles for biasing various illustrated devices, as further explored below. QVCO 10 also includes two symmetric oscillating circuits 20 and 50, which are coupled together so as to lock the operation and oscillating signals of the two in quadrature, as will be explained later. Since circuits 20 and 50 are symmetric, the following discussion will detail circuit 20 by way of example, followed by an overview of the comparable circuit 50.
Oscillating circuit 20 includes a first inductor 22 and a second inductor 24, each having a respective first terminal 22T1 and 24T1 connected to receive a fixed voltage potential, shown as VDD. A second terminal 22T2 of inductor 22 is connected to a node 26, which is also connected to a drain of an nMOS transistor 28, and a second terminal 24T2 of inductor 24 is connected to a node 30, which is also connected to a drain of an nMOS transistor 32. The sources of nMOS transistors 28 and 32 are connected to a node 34, and the gates of nMOS transistors 28 and 32 are cross-coupled, that is, the gate of nMOS transistor 28 is connected to the drain of nMOS transistor 32, and the gate of nMOS transistor 32 is connected to the drain of nMOS transistor 28. Node 34 is connected to the drain of an nMOS transistor 36, which has its gate connected to bias control circuitry 12 and its source connected to a lower reference potential, shown by way of example as ground.
Oscillating circuit 20 also includes two additional nMOS transistors 38 and 40, each of which is connected for parallel injection of respective output signals provided by oscillating circuit 50, as is now explored. The drain of nMOS transistor 38 is connected to node 26, and the source of nMOS transistor 38 is connected to a node 42. The gate of nMOS transistor 38 is connected to receive an oscillating output signal Q− from oscillating circuit 50 and a DC bias signal from bias control circuitry 12, both via a decoupling circuit 44. Decoupling circuit 44 may be constructed in various fashions known in the art, so by convention and for sake of example this is shown in FIG. 1 as the AC signal of Q− connected through a capacitor C and the DC bias from circuitry 12 connected through a resistor R. The drain of nMOS transistor 40 is connected to node 30, and the source of nMOS transistor 40 is connected to node 42. The gate of nMOS transistor 40 is connected to receive an oscillating output signal Q+ from oscillating circuit 50 and a DC bias signal, both via a decoupling circuit 46. The illustration of decoupling circuit 46 is the same as provided for decoupling circuit 44, where here the AC signal of Q+ is connected through a capacitor C and the DC bias from circuitry 12 is connected through a resistor R. An nMOS transistor 48 has its drain connected to node 42, its source connected to the lower reference potential (e.g., ground), and its gate to bias control circuitry 12. Lastly, note that node 26 provides a first oscillating output signal I+, and node 30 provides a second oscillating output signal I−, where these two signals are ideally 180 degrees apart, as also further detailed later.
As introduced above, oscillating circuit 50 is comparable in devices and connections with respect to oscillating circuit 20. As now will be appreciated, however, oscillating circuit 50 provides the quadrature Q outputs and operates in response to the in-phase I inputs (as output from oscillating circuit 20). Specifically, oscillating circuit 50 includes a first inductor 52 and a second inductor 54, each having a respective first terminal 52T1 and 54T1 connected to receive the fixed voltage potential, VDD. A second terminal 52T2 of inductor 52 is connected to a node 56, which is also connected to a drain of an nMOS transistor 58, and a second terminal 54T2 of inductor 54 is connected to a node 60, which is also connected to a drain of an nMOS transistor 62. The sources of nMOS transistors 58 and 62 are connected to a node 64, and the gates of nMOS transistors 58 and 62 are cross-coupled, that is, the gate of nMOS transistor 58 is connected to the drain of nMOS transistor 62, and the gate of nMOS transistor 62 is connected to the drain of nMOS transistor 58. Node 64 is connected to the drain of an nMOS transistor 66, which has its gate connected to bias control circuitry 12 and its source connected to the lower reference potential (e.g., ground).
Oscillating circuit 50 also includes two additional nMOS transistors 68 and 70, each of which is connected for parallel injection of the respective output signals of oscillating circuit 20, as is now explored. The drain of nMOS transistor 68 is connected to node 56, and the source of nMOS transistor 68 is connected to a node 72. The gate of nMOS transistor 68 is connected to receive an oscillating output signal I+ from oscillating circuit 20 and a DC biasing signal, both via a decoupling circuit 74. Thus, as in the case of above-described decoupling circuits, the AC signal of I+ is connected through a capacitor C and the DC bias from circuitry 12 is connected through a resistor R. The drain of nMOS transistor 70 is connected to node 60, and the source of nMOS transistor 70 is connected to node 72. The gate of nMOS transistor 70 is connected to receive an oscillating output signal I− from oscillating circuit 20 and a DC biasing signal, both via a decoupling circuit 76. Thus, as in the case of above-described decoupling circuits, the AC signal of I− is connected through a capacitor C and the DC bias from circuitry 12 is connected through a resistor R. An nMOS transistor 78 has its drain connected to node 72, its source connected to the lower reference potential (e.g., ground), and its gate to bias control circuitry 12. Lastly, note that node 56 provides a first oscillating output signal Q+, and node 60 provides a second oscillating output signal Q−, where these two signals are ideally 180 degrees apart, as also further detailed later.
The operation of QVCO 10 is now generally described for context in this document, with additional aspects readily known or ascertainable by one skilled in the art. Looking first to oscillating circuit 20, in general an oscillating loop may be observed with respect to inductors 22 and 24 and nMOS transistors 28 and 32. Particularly, with this loop, charge oscillates between the inductance and inherent transistor capacitance, and while resistance also exists in the circuit that would tend to diminish the response of the circuit, as known in the VCO art the cross-coupling of the gates of nMOS transistors 28 and 32 provides a negative trans-conductance, sometimes also referred to as a −R, so as to compensate for this resistance and to maintain the loop in oscillation. Thus, this loop provides the oscillating signals I+ and I− which, as charge is exchanged in the loop and given the cross-coupling of nMOS transistors 28 and 32, causes the drain of one of those transistors to rise in voltage while the other falls in complementary fashion, and vice versa, such that I+ and I− at those drains are anti-phase signals, that is, they remain 180 degrees (i.e., one half-period) apart from one another. In addition to the above-described loop operation, note also that each of nMOS transistors 38 and 40, in parallel with the combination of nMOS transistors 28 and 32, injects or modulates into the loop the signals Q− and Q+, respectively. Specifically, bias control circuitry 12 maintains nMOS transistor 48 on as a current source while applying a DC biasing voltage to the gates of each of nMOS transistors 38 and 40, so each of nMOS transistors 38 and 40 remains on and conducts current further in response to the rise and fall of the respective inputs Q− and Q+. Thus, the total current through nMOS transistors 38 and 40 remains constant (i.e., equal to that of the sourcing nMOS transistor 48), whereby as the current through one of those transistors increases the current through the other decreases, and vice versa, in a complementary fashion, thus maintaining the total.
Looking to oscillating circuit 50, it generally operates in the same way as oscillating circuit 20, albeit in a phase-shifted fashion, and the reader is assumed familiar therefore with the previous discussion which is now briefly summarized with respect to the comparable circuit 50. Generally, the loop of inductors 52 and 54 and nMOS transistors 58 and 62 oscillates and the opposing complementary potential at the drains of those transistors provides the antiphase output pairing of Q+ and Q−. Further, that loop is modulated by the injection of I+ and I−, from circuit 20, into the respective gates of nMOS transistors 68 and 70, with each of those transistors always on in response to the DC bias at their gates and together conducting a total current matching that sourced by nMOS transistor 78, whereby as the current through one of those transistors increases the current through the other decreases, and vice versa, in a complementary fashion, thus maintaining the total.
Having described the general operation of circuits 20 and 50, note further that such operation locks oscillating circuit 20 in quadrature with respect to oscillating circuit 50. As noted above, in each circuit the outputs (i.e., either Q+ and Q− or I+ and I−) are antiphase signals. By virtue of the cross-coupling, two tanks and the devices being identical and the magnitude of the phasor current in the two tanks to be equal, each of the four outputs will remain in quadrature, 90 degrees apart.
FIG. 2 illustrates a schematic of a prior art series injection QVCO shown generally at 80. QVCO 80 includes bias control circuitry 110 that may be constructed according to known principles for biasing various illustrated devices, as further explored below. QVCO 80 also includes two symmetric oscillating circuits 90 and 120, which are coupled together so as to lock the operation and oscillating signals of the two in quadrature, as will be explained later. Since circuits 90 and 120 are symmetric, the following discussion will detail circuit 90 by way of example, followed by an overview of the comparable circuit 120.
Oscillating circuit 90 includes a first inductor 92 and a second inductor 94, each having a respective first terminal 92T1 and 94T1 connected to receive a fixed voltage potential, shown as VDD. A second terminal 92T2 of inductor 92 is connected to a node 96, which is also connected to a drain of an nMOS transistor 98, and a second terminal 94T2 of inductor 94 is connected to a node 100, which is also connected to a drain of an nMOS transistor 102. The source of nMOS transistor 98 is connected to a node 104, and the source of nMOS transistor 102 is connected to a node 106. The gates of nMOS transistors 98 and 102 are cross-coupled, that is, the gate of nMOS transistor 98 is connected to the drain of nMOS transistor 102, and the gate of nMOS transistor 102 is connected to the drain of nMOS transistor 98. Node 104 is connected to the drain of an nMOS transistor 108, which has its gate connected to a decoupling circuit 110 and its source connected to a node 112. Decoupling circuit 110 follows the same convention of FIG. 1, so again an AC signal of Q− is connected through a capacitor C and the DC bias from circuitry 110 is connected through a resistor R, both to the gate of nMOS transistor 108. Node 106 is connected to the drain of an nMOS transistor 114, which has its gate connected to a decoupling circuit 116 and its source connected to node 112. Decoupling circuit 116 connects Q+ through a capacitor C, and the DC bias from circuitry 110 through a resistor R, to the gate of nMOS transistor 114. Node 112 is connected to the drain of an nMOS transistor 118, which has its source connected to ground and its gate connected to bias control circuitry 110.
As introduced above, oscillating circuit 120 is comparable in devices and connections with respect to oscillating circuit 90. Oscillating circuit 120, however, provides the quadrature Q outputs and operates in response to the in-phase I inputs as output from oscillating circuit 90. Specifically, oscillating circuit 120 includes a first inductor 122 and a second inductor 124, each having a respective first terminal 122T1 and 124T1 connected to receive the fixed voltage potential, VDD. A second terminal 122T2 of inductor 122 is connected to a node 126, which is also connected to a drain of an nMOS transistor 128, and a second terminal 124T2 of inductor 124 is connected to a node 130, which is also connected to a drain of an nMOS transistor 132. The source of nMOS transistor 128 is connected to a node 134, and the source of nMOS transistor 132 is connected to a node 136. The gates of nMOS transistors 128 and 132 are cross-coupled, that is, the gate of nMOS transistor 128 is connected to the drain of nMOS transistor 132, and the gate of nMOS transistor 132 is connected to the drain of nMOS transistor 128. Node 134 is connected to the drain of an nMOS transistor 138, which has its gate connected to a decoupling circuit 140 and its source connected to a node 142. Decoupling circuit 140 couples an AC signal of I+ through a capacitor C, and the DC bias from circuitry 110 through a resistor R, to the gate of nMOS transistor 138. Node 136 is connected to the drain of an nMOS transistor 144, which has its gate connected to a decoupling circuit 146 and its source connected to node 142. Decoupling circuit 146 connects I− through a capacitor C, and the DC bias from circuitry 110 through a resistor R, to the gate of nMOS transistor 144. Node 142 is connected to the drain of an nMOS transistor 148, which has its source connected to ground and its gate connected to bias control circuitry 110.
The operation of QVCO 80 is now generally described for context in this document, with additional aspects readily known or ascertainable by one skilled in the art.
Looking first to oscillating circuit 90, in general an oscillating loop may be observed with respect to inductors 92 and 94, cross-coupled nMOS transistors 98 and 102, and the nMOS transistors 108 and 114 respectively in series with nMOS transistors 98 and 102. Specifically, bias control circuitry 110 maintains nMOS transistor 118 on as a current source and applies a DC biasing voltage to the gates of each of nMOS transistors 108 and 114, so each of nMOS transistors 108 and 114 remains on and conducts current—moreover, as these transistors are in series, respectively, with nMOS transistors 98 and 102, those transistors also commute the same current, respectively, as nMOS transistors 108 and 114, with the sum total current through all four transistors remaining constant and equal to that sourced by nMOS transistor 118. Moreover, with this loop, charge oscillates between the inductance and inherent transistor capacitance, with the cross-coupling of the gates of nMOS transistors 98 and 102 providing a negative trans-conductance to maintain the loop in oscillation. Thus, this loop provides the antiphase oscillating signals I+ and I−, as charge is exchanged in the loop. Further, nMOS transistors 98 and 102 modulate the loop oscillation by injecting the phases of Q− and Q+, respectively, into the oscillating signal.
Looking to oscillating circuit 120, it generally operates in the same way as oscillating circuit 90, albeit in phase-shifted fashion. Generally, bias control circuitry 110 maintains nMOS transistor 148 on as a current source and applies a DC biasing voltage to the gates of each of nMOS transistors 138 and 144, so each of nMOS transistors 138 and 144 remains on and conducts current—moreover, as these transistors are in series, respectively with nMOS transistors 128 and 132, those transistors also commute the same current, respectively, as nMOS transistors 138 and 144, with the sum total current through all four transistors remaining constant and equal to that sourced by nMOS transistor 148. Moreover, with this loop, charge oscillates between the inductance and inherent transistor capacitance, with the cross-coupling of the gates of nMOS transistors 128 and 132 providing a negative trans-conductance to maintain the loop in oscillation. Thus, this loop provides the antiphase oscillating signals Q+ and Q−, as charge is exchanged in the loop. Further, nMOS transistors 138 and 144 modulate the loop oscillation by injecting the phases of I+ and I−, respectively, into the oscillating signal.
Having described the general operation of circuits 90 and 120, note further that such operation locks oscillating circuit 90 in quadrature with respect to oscillating circuit 120. By virtue of the cross-coupling, two tanks and the devices being identical and the magnitude of the phasor current in the two tanks to be equal, each of the four outputs will remain in quadrature, 90 degrees apart.
While the above and related approaches have served various needs in the prior art, they also provide various drawbacks. For example, the present inventors have observed that the transistors injecting I/Q signals are always on, thereby causing a considerable amount of power consumption. In addition, such a configuration introduces undesirable flicker noise into the QVCO, which also gets upconverted to the frequency of interest/oscillation, thereby adding noise into the system that uses the oscillating signal.
Given the preceding, the present inventors seek to improve upon the prior art, as further detailed below.